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1 ltc3716 applicatio s u typical applicatio u features the ltc ? 3716 is a 2-phase, vid programmable, synchro- nous step-down switching regulator controller that drives two n-channel external power mosfet stages in a fixed fre- quency architecture. the 2-phase controller drives its two output stages out of phase at frequencies up to 300khz to minimize the rms ripple currents in both input and output capacitors. the 2-phase technique effectively multiplies the fundamental frequency by two, improving transient re- sponse while operating each channel at an optimum fre- quency for efficiency. thermal design is also simplified. an operating mode select pin (fcb) can be used to regu- late a secondary winding or select among three modes including burst mode tm operation for highest efficiency. an internal differential amplifier provides true remote sensing of the regulated supplys positive and negative output ter- minals as required in high current applications. the run/ss pin provides soft-start and optional timed, short-circuit shutdown. current foldback limits mosfet dissipation during short-circuit conditions when the overcurrent latchoff is disabled. opti-loop compensation allows the transient response to be optimized for a wide range of output capacitors and esr values. 2-phase, 5-bit vid, current mode, high efficiency, synchronous step-down switching regulator february 2001 , ltc and lt are registered trademarks of linear technology corporation. opti-loop and burst mode are trademarks of linear technology corporation. figure 1. high current dual phase step-down converter n mobile computer cpu supply n output stages operate antiphase reducing input and output capacitance requirements and power supply induced noise n dual input supply capability for load sharing n 5-bit mobile vid code: v out = 0.6v to 1.75v n current mode control ensures current sharing n true remote sensing differential amplifier n power good output voltage monitor n opti-loop tm compensation minimizes c out n three operational modes: pwm, burst and cycle skip n programmable fixed frequency: 150khz to 300khz n 1% output voltage accuracy n wide v in range: 4v to 36v operation n adjustable soft-start current ramping n internal current foldback and short-circuit shutdown n overvoltage soft latch eliminates nuisance trips n supports active voltage positioning n available in 36-lead narrow ssop package 3716 f01 tg1 boost1 sw1 bg1 pgnd sense1 + sense1 tg2 boost2 sw2 bg2 intv cc sense2 + sense2 v in run/ss fcb v diffout i th attenin attenout eain vid0?id4 v os v os + ltc3716 sgnd pgood 0.1 f 220pf 5 vid bits s s 3.3k + 10 f 35v 4 + c out 1000 f 4v 2 v out 0.6v to 1.75v 40a 1 h 0.002 0.002 v in 5v to 28v 1 h 0.47 f 0.47 f 10 f 4 3 2 1 4 3 2 1 final electrical specifications information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. descriptio u
2 ltc3716 order part number ltc3716eg absolute axi u rati gs w ww u package/order i for atio uu w t jmax = 125 c, q ja = 85 c/w consult factory for parts specified with wider operating temperature ranges. electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 15v, v bias = 5v, v run/ss = 5v unless otherwise noted. (note 1) input supply voltage (v in ).........................36v to C 0.3v topside driver voltages (boost1,2) .........42v to C 0.3v switch voltage (sw1, 2) .............................36v to C 5 v sense1 + , sense2 + , sense1 C , sense2 C voltages ................... (1.1)intv cc to C 0.3v eain, v os + , v os C , extv cc , intv cc , run/ss, v bias , attenin, attenout, pgood, ampmd, vid0Cvid4, voltages ...............................7v to C 0.3v boosted driver voltage (boost-sw) .......... 7v to C 0.3v pllfltr, pllin, v diffout , fcb voltages ................................... intv cc to C 0.3v i th voltage ................................................2.7v to C 0.3v peak output current <1 m s(tgl1,2, bg1,2) ................ 3a intv cc rms output current ................................ 50ma operating ambient temperature range (note 2) .............................................. C 40 c to 85 c junction temperature (note 3) ............................. 125 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 top view g package 36-lead plastic ssop 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 run/ss sense1 + sense1 eain pllfltr pllin fcb i th sgnd v diffout v os v os + sense2 sense2 + attenout attenin vid0 vid1 pgood tg1 sw1 boost1 v in bg1 extv cc intv cc pgnd bg2 boost2 sw2 tg2 ampmd v bias vid4 vid3 vid2 symbol parameter conditions min typ max units main control loop v eain regulated feedback voltage i th voltage = 1.2v; measured at v eain (note 4) l 0.594 0.600 0.606 v v sensemax maximum current sense threshold v sense C = 5v l 62 75 88 mv v sense C = 1.25v 62 75 88 mv i ineain feedback current (note 4) C 5 C 50 na v loadreg output voltage load regulation (note 4) measured in servo loop, d i th voltage: 1.2v to 0.7v l 0.1 0.5 % measured in servo loop, d i th voltage: 1.2v to 2v l C 0.1 C 0.5 % v reflnreg reference voltage line regulation v in = 3.6v to 30v (note 4) 0.002 0.02 %/v v fcb forced continuous threshold l 0.57 0.6 0.63 v i fcb forced continuous current C 0.17 C 1 m a v binhibit burst inhibit (constant frequency) measured at fcb pin 4.3 4.8 v threshold v ovl output overvoltage threshold measured at v eain l 0.64 0.66 0.68 v uvlo undervoltage lockout v in ramping down 3 3.33 4 v g m transconductance amplifier g m i th = 1.2v, sink/source 5 m a (note 4) 3 mmho g mol transconductance amplifier gain i th = 1.2v, (g m z l ; no ext load) (note 4) 1.5 v/mv
3 ltc3716 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 15v, v bias = 5v, v run/ss = 5v unless otherwise noted. symbol parameter conditions min typ max units i q input dc supply current (note 5) normal mode 1.2 ma shutdown v run/ss = 0v 20 40 m a i run/ss soft-start charge current v run/ss = 1.9v C 0.5 C1.2 m a v run/ss run/ss pin on threshold v run/ss rising 1.0 1.5 1.9 v v run/sslo run/ss pin latchoff arming v run/ss rising from 3v 4.1 4.5 v i scl run/ss discharge current soft short condition v eain = 0.5v, v run/ss = 4.5v 0.5 2 4 m a i sdlho shutdown latch disable current v eain = 0.5v 1.6 5 m a i sense total sense pins source current each channel: v sense1 C , 2 C = v sense1 + , 2 + = 0v C 85 C 60 m a df max maximum duty factor in dropout 98 99.5 % top gate transition time: (note 6) tg1, 2 t r rise time c load = 3300pf 30 90 ns tg1, 2 t f fall time c load = 3300pf 40 90 ns bottom gate transition time: (note 6) bg1, 2 t r rise time c load = 3300pf 30 90 ns bg1, 2 t f fall time c load = 3300pf 20 90 ns tg/bg t 1d top gate off to bottom gate on delay c load = 3300pf each driver (note 6) 90 ns synchronous switch-on delay time bg/tg t 2d bottom gate off to top gate on delay c load = 3300pf each driver (note 6) 90 ns top switch-on delay time t on(min) minimum on-time tested with a square wave (note 7) 180 ns internal v cc regulator v intvcc internal v cc voltage 6v < v in < 30v, v extvcc = 4v 4.8 5.0 5.2 v v ldo int intv cc load regulation i cc = 0 to 20ma, v extvcc = 4v 0.2 1.0 % v ldo ext extv cc voltage drop i cc = 20ma, v extvcc = 5v 80 160 mv v extvcc extv cc switchover voltage i cc = 20ma, extv cc ramping positive l 4.5 4.7 v v ldohys extv cc switchover hysteresis i cc = 20ma, extv cc ramping negative 0.2 v vid parameters v bias operating supply voltage range 2.7 5.5 v r atten resistance between attenin 10 k w and attenout pins atten err resistive divider error l C 0.25 0.25 % r pullup vid0 to vid4 pull-up resistance (note 8) 40 k w vid thl, thh vid0 to vid4 logic threshold v il 2.7v < v bias < 5.5v; low input 0.4 v v il 2.7v < v bias < 5.5v; high input 1.6 v vid leak vid0 to vid4 leakage v bias < vid0Cvid4 < 7v 1 m a oscillator and phase-locked loop f nom nominal frequency v pllfltr = 1.2v 190 220 250 khz f low lowest frequency v pllfltr = 0v 120 140 160 khz f high highest frequency v pllfltr 3 2.4v 280 310 360 khz r pllin pllin input resistance 50 k w i pllfltr phase detector output current sinking capability f pllin < f osc C15 m a sourcing capability f pllin > f osc 15 m a r relphs controller 2-controller 1 phase 180 deg
4 ltc3716 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 15v, v bias = 5v, v run/ss = 5v unless otherwise noted. note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 7: the minimum on-time condition corresponds to the on inductor peak-to-peak ripple current 3 40% i max (see minimum on-time considerations in the applications information section). note 8: each built-in pull-up resistor attached to the vid inputs also has a series diode to allow input voltages higher than the vidv cc supply without damage or clamping (see the applications information section). note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the ltc3716 is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C 40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: ltc3716eg: t j = t a + (p d ? 85 c/w) note 4: the ltc3716 is tested in a feedback loop that servos v ith to a specified voltage and measures the resultant v eain . symbol parameter conditions min typ max units pgood output v pgl pgood voltage low i pgood = 2ma 0.1 0.3 v i pgood pgood leakage current v pgood = 5v 1 m a v pg pgood trip level, either controller v eain with respect to set output voltage v eain ramping negative C 8 C 10 C 12 % v eain ramping positive 8 10 12 % differential amplifier/op amp gain block a da differential amplifier gain v ampmd = 0v 0.995 1 1.005 v/v cmrr da common mode rejection ratio 0v < v cm < 5v; v ampmd = 0v 46 55 db r in input resistance measured at v os + input; v ampmd = 0v 80 k w v os input offset voltage op amp mode; v cm = 2.5v, v ampmd = 5v 6 mv v diffout = 5v; i diffout = 1ma i b input bias current op amp mode; v ampmd = 5v 30 200 na a ol open loop dc gain op amp mode; 0.7v v diffout < 10v, v ampmd = 5v 5000 v/mv v cm common mode input voltage range op amp mode; v ampmd = 5v 0 3 v cmrr oa common mode rejection ratio op amp mode; 0v < v cm < 3v, v ampmd = 5v 70 90 db psrr oa power supply rejection ratio op amp mode; 6v < v in < 30v, v ampmd = 5v 70 90 db i cl maximum output current op amp mode; v diffout = 0v, v ampmd = 5v 10 35 ma v omax maximum output voltage op amp mode; i diffout = 1ma, v ampmd = 5v 10 11 v gbw gain-bandwidth product op amp mode; i diffout = 1ma, v ampmd = 5v 2 mhz sr slew rate op amp mode; r l = 2k, v ampmd = 5v 5 v/ m s
5 ltc3716 typical perfor a ce characteristics uw supply current vs input voltage and mode extv cc voltage drop intv cc and extv cc switch voltage vs temperature input voltage (v) 05 0 supply current ( a) 400 1000 10 20 25 3716 g04 200 800 600 15 30 35 on shutdown current (ma) 0 extv cc voltage drop (mv) 150 200 250 40 3716 g05 100 50 0 10 20 30 50 temperature ( c) ?0 intv cc and extv cc switch voltage (v) 4.95 5.00 5.05 25 75 3716 g06 4.90 4.85 ?5 0 50 100 125 4.80 4.70 4.75 intv cc voltage extv cc switchover threshold maximum current sense threshold vs percent of nominal output voltage (foldback) internal 5v ldo line reg maximum current sense threshold vs duty factor input voltage (v) 0 4.8 4.9 5.1 15 25 3716 g07 4.7 4.6 510 20 30 35 4.5 4.4 5.0 intv cc voltage (v) i load = 1ma duty factor (%) 0 0 v sense (mv) 25 50 75 20 40 60 80 3716 g08 100 percent of nominal output voltage (%) 0 v sense (mv) 40 50 60 100 3716 g09 30 20 0 25 50 75 10 80 70 efficiency vs load current (3 operating modes) (figure 13) load current (a) 0 efficiency (%) 10 30 40 50 100 70 0.01 0.1 1 3716 g01 20 80 90 60 100 10 forced continuous mode burst mode operation v in = 5v v out = 1.6v freq = 200khz constant frequency (burst disable) efficiency vs load current (figure 13) load current (a) 0.1 efficiency (%) 100 80 60 40 20 0 3716 g02 1 10 100 v out = 1.6v v extvcc = 0v freq = 200khz v fcb = 0v v in = 5v v in = 8v v in = 12v v in = 20v input voltage (v) 5 efficiency (%) 70 80 3716 g03 60 50 10 v out = 1.6v 15 20 100 90 i out = 20a efficiency vs input voltage (figure 13)
6 ltc3716 typical perfor a ce characteristics uw load regulation v ith vs v run/ss (soft-start) sense pins total source current load current (a) 0 normalized v out (%) 0.2 0.1 4 3716 g13 0.3 0.4 1 2 3 5 0.0 fcb = 0v v in = 15v figure 1 v run/ss (v) 0 0 v ith (v) 0.5 1.0 1.5 2.0 2.5 1 234 3716 g14 56 v osense = 0.7v v sense common mode voltage (v) 0 i sense ( a) 0 3716 g15 ?0 100 24 50 100 6 maximum current sense threshold vs temperature temperature ( c) 50 ?5 70 v sense (mv) 74 80 0 50 75 3716 g16 72 78 76 25 100 125 run/ss current vs temperature temperature ( c) ?0 25 0 run/ss current ( a) 0.2 0.6 0.8 1.0 75 100 50 1.8 3716 g17 0.4 0 25 125 1.2 1.4 1.6 soft-start up (figure 13) v ith 1v/div v out 2v/div v run/ss 2v/div 100ms/div 3716 g18 maximum current sense threshold vs v run/ss (soft-start) maximum current sense threshold vs sense common mode voltage current sense threshold vs i th voltage common mode voltage (v) 0 v sense (mv) 72 76 80 4 3716 g11 68 64 60 1 2 3 5 v ith (v) 0 v sense (mv) 30 50 70 90 2 3716 g12 10 ?0 20 40 60 80 0 ?0 ?0 0.5 1 1.5 2.5 v run/ss (v) 0 0 v sense (mv) 20 40 60 80 1234 3716 g10 56 v sense(cm) = 1.6v
7 ltc3716 typical perfor a ce characteristics uw current sense pin input current vs temperature extv cc switch resistance vs temperature oscillator frequency vs temperature temperature ( c) ?0 25 25 current sense input current ( a) 29 35 0 50 75 3716 g20 27 33 31 25 100 125 v out = 5v temperature ( c) ?0 25 0 extv cc switch resistance ( ) 4 10 0 50 75 3716 g21 2 8 6 25 100 125 temperature ( c) ?0 200 250 350 25 75 3716 g22 150 100 ?5 0 50 100 125 50 0 300 frequency (khz) v freqset = 5v v freqset = open v freqset = 0v undervoltage lockout vs temperature temperature ( c) ?0 undervoltage lockout (v) 3.40 3.45 3.50 25 75 3716 g23 3.35 3.30 ?5 0 50 100 125 3.25 3.20 v run/ss shutdown latch thresholds vs temperature temperature ( c) ?0 25 0 shutdown latch thresholds (v) 0.5 1.5 2.0 2.5 75 100 50 4.5 3716 g24 1.0 0 25 125 3.0 3.5 4.0 latch arming latchoff threshold load step (figure 13) i cc 4a/div v cc 50mv/div 25 m s/div 3716 g19 fcb = 0v v out(ac) 20mv/div i l1 1a/div i l2 1a/div 10 m s/div 3716 g25 v in = 15v, v out = 1.6v, i l = 200ma rms burst mode operation (figure 13) constant frequency mode (figure 13) v out(ac) 20mv/div i l1 1a/div i l2 1a/div 2 m s/div 3716 g26 v in = 15v, v out = 1.6v, i l = 400ma rms fcb = intv cc fcb = open v in = 15v, v out = 1.25v, slew rate = 30a/ m s
8 ltc3716 pi fu ctio s uuu run/ss (pin 1): combination of soft-start, run control input and short-circuit detection timer. a capacitor to ground at this pin sets the ramp time to full current output. forcing this pin below 0.8v causes the ic to shut down all internal circuitry. all functions are disabled in shutdown. sense1 + , sense2 + (pins 2,14): the (+) input to each differential current comparator. the i th pin voltage and built-in offsets between sense C and sense + pins in conjunction with r sense set the current trip threshold. sense1 C , sense2 C (pins 3,13): the (C) input to the differential current comparators. eain (pin 4): input to the error amplifier that compares the feedback voltage to the internal 0.6v reference voltage. this pin is normally connected to a resistive divider from the output of the differential amplifier (diffout). pllfltr (pin 5): the phase-locked loops lowpass filter is tied to this pin. alternatively, this pin can be driven with an ac or dc voltage source to vary the frequency of the internal oscillator. pllin (pin 6): external synchronization input to phase detector. this pin is internally terminated to sgnd with 50k w . the phase-locked loop will force the rising top gate signal of controller 1 to be synchronized with the rising edge of the pllin signal. fcb (pin 7): forced continuous control input. this input acts on both output stages and can be used to regulate a secondary winding. pulling this pin below 0.6v will force continuous synchronous operation. do not leave this pin floating without a decoupling capacitor. i th (pin 8): error amplifier output and switching regula- tor compensation point. both current comparators thresh- olds increase with this control voltage. the normal voltage range of this pin is from 0v to 2.4v sgnd (pin 9): signal ground. this pin is common to both controllers. route separately to the pgnd pin. v diffout (pin 10): output of a differential amplifier. this pin provides true remote output voltage sensing. v diffout normally drives an external resistive divider that sets the output voltage. v os C , v os + (pins 11, 12): inputs to an operational ampli- fier. internal precision resistors configure it as a differen- tial amplifier whose output is v diffout . attenout (pin 15): voltage feedback signal resistively divided according to the vid programming code. attenin (pin 16): the input to the vid controlled resis- tive divider. vid0Cvid4 (pins 17,18, 19, 20, 21): vid control logic input pins. v bias (pin 22): supply pin for the vid control circuit. ampmd (pin 23): this logic input pin controls the connections of internal precision resistors that configure the operational amplifier as a unity-gain differential ampli- fier. tg2, tg1 (pins 24, 35): high current gate drives for top n-channel mosfets. these are the outputs of floating drivers with a voltage swing equal to intv cc superim- posed on the switch node voltage sw. sw2, sw1 (pins 25, 34): switch node connections to inductors. voltage swing at these pins is from a schottky diode (external) voltage drop below ground to v in . boost2, boost1 (pins 26, 33): bootstrapped supplies to the topside floating drivers. external capacitors are connected between the boost and sw pins, and schottky diodes are connected between the boost and intv cc pins. bg2, bg1 (pins 27, 31): high current gate drives for bottom n-channel mosfets. voltage swing at these pins is from ground to intv cc . pgnd (pin 28): driver power ground. connect to sources of bottom n-channel mosfets and the (C) terminals of c in . intv cc (pin 29): output of the internal 5v linear low dropout regulator and the extv cc switch. the driver and control circuits are powered from this voltage source. decouple to power ground with a 1 m f ceramic capacitor placed directly adjacent to the ic and minimum of 4.7 m f additional tantalum or other low esr capacitor. extv cc (pin 30): external power input to an internal switch. this switch closes and supplies intv cc, bypass- ing the internal low dropout regulator whenever extv cc is higher than 4.7v. see extv cc connection in the applica- tions information section. do not exceed 7v on this pin and ensure v extvcc v intvcc .
9 ltc3716 fu ctio al diagra uu w pi fu ctio s uuu v in (pin 32): main supply pin. should be closely de- coupled to the ics signal ground pin. pgood (pin 36): open-drain logic output. pgood is pulled to ground when the voltage on the eain pin is not within 10% of its set point. switch logic 0.60v 4.8v 5v v in clk2 to second channel clk1 + + v ref internal supply extv cc intv cc sgnd + 5v ldo reg sw shdn 0.55v top boost tg c b c in d1 d b pgnd bot bg intv cc intv cc v in + 3716 fbd eain v fb drop out det run soft start bot fcb top on s r q q oscillator pllfltr 50k ea 0.66v 0.60v ov 1.2 a 6v + r c 5v fb rst shdn run/ss i th c c c ss 5v fb 0.86v slope comp + + sense sense + intv cc 30k 45k 2.4v 45k r sense 30k i 1 i 2 b attenin 10k r1 vid0 attenout vid1 vid2 vid3 vid4 typical all vid pins 40k v bias phase det pllin duplicate for second controller channel c c2 + + c out v out + f in r lp c lp + diffout ampmd v os + v os 0.54v 0.66v + + eain pgood 5-bit vid decoder + + 4.5v 0.18 a + fcb 3v fcb l a1 0v position 4 3 2 1
10 ltc3716 operatio u (refer to functional diagram) main control loop the ltc3716 uses a constant frequency, current mode step-down architecture with the two output stages oper- ating 180 degrees out of phase. during normal operation, each top mosfet is turned on when the clock for that channel sets the rs latch, and turned off when the main current comparator, i 1 , resets the rs latch. the peak inductor current at which i 1 resets the rs latch is con- trolled by the voltage on the i th pin, which is the output of error amplifier ea. the eain pin receives the voltage feedback signal, which is compared to the internal refer- ence voltage by the ea. when the load current increases, it causes a slight decrease in v eain relative to the 0.6v reference, which in turn causes the i th voltage to increase until the average inductor current matches the new load current. after the top mosfet has turned off, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by current comparator i 2 , or the beginning of the next cycle. the top mosfet drivers are biased from floating boot- strap capacitor c b , which normally is recharged during each off cycle through an external diode when the top mosfet turns off. as v in decreases to a voltage close to v out , the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detector de- tects this and forces the top mosfet off for about 500ns every tenth cycle to allow c b to recharge. the main control loop is shut down by pulling the run/ ss pin low. releasing run/ss allows an internal 1.2 m a current source to charge soft-start capacitor c ss . when c ss reaches 1.5v, the main control loop is enabled with the i th voltage clamped at approximately 30% of its maximum value. as c ss continues to charge, the i th pin voltage is gradually released allowing normal, full-current operation. low current operation the fcb pin is a multifunction pin providing two func- tions: 1) to provide regulation for a secondary winding by temporarily forcing continuous pwm operation on both controllers; and 2) select between two modes of low current operation. when the fcb pin voltage is below 0.6v, the controller forces continuous pwm current mode operation. in this mode, the top and bottom mosfets are alternately turned on to maintain the output voltage independent of direction of inductor current. when the fcb pin is below v intvcc C 2v but greater than 0.6v, the controller enters burst mode operation. burst mode operation sets a minimum output current level before inhibiting the top switch and turns off the synchro- nous mosfet(s) when the inductor current goes nega- tive. this combination of requirements will, at low currents, force the i th pin below a voltage threshold that will temporarily inhibit turn-on of both output mosfets until the output voltage drops. there is 60mv of hysteresis in the burst comparator b tied to the i th pin. this hysteresis produces output signals to the mosfets that turn them on for several cycles, followed by a variable sleep interval depending upon the load current. the resultant output voltage ripple is held to a very small value by having the hysteretic comparator after the error amplifier gain block. constant frequency operation when the fcb pin is tied to intv cc , burst mode operation is disabled and a forced minimum peak output current requirement is removed. this provides constant frequency, discontinuous (preventing reverse inductor current) cur- rent operation over the widest possible output current range. this constant frequency operation is not as efficient as burst mode operation, but does provide a lower noise, constant frequency operating mode down to approxi- mately 1% of designed maximum output current. continuous current (pwm) operation tying the fcb pin to ground will force continuous current operation. this is the least efficient operating mode, but may be desirable in certain applications. the output can source or sink current in this mode. when sinking current while in forced continuous operation, current will be forced back into the main power supply potentially boost- ing the input supply to dangerous voltage levels beware!
11 ltc3716 operatio u (refer to functional diagram) frequency synchronization the phase-locked loop allows the internal oscillator to be synchronized to an external source via the pllin pin. the output of the phase detector at the pllfltr pin is also the dc frequency control input of the oscillator that operates over a 140khz to 310khz range corresponding to a dc voltage input from 0v to 2.4v. when locked, the pll aligns the turn on of the top mosfet to the rising edge of the synchronizing signal. when pllin is left open, the pllfltr pin goes low, forcing the oscillator to minimum frequency. input capacitance esr requirements and efficiency losses are substantially reduced because the peak current drawn from the input capacitor is effectively divided by two and power loss is proportional to the rms current squared. a two stage, single output voltage implementation can reduce input path power loss by 75% and radically reduce the required rms current rating of the input capacitor(s). intv cc /extv cc power power for the top and bottom mosfet drivers and most of the ic circuitry is derived from intv cc . when the extv cc pin is left open, an internal 5v low dropout regulator supplies intv cc power. if the extv cc pin is taken above 4.8v, the 5v regulator is turned off and an internal switch is turned on connecting extv cc to intv cc . this allows the intv cc power to be derived from a high efficiency external source such as the output of the regu- lator itself or a secondary winding, as described in the applications information section. an external schottky diode can be used to minimize the voltage drop from extv cc to intv cc in applications requiring greater than the specified intv cc current. voltages up to 7v can be applied to extv cc for additional gate drive capability. differential amplifier this amplifier provides true differential output voltage sensing. sensing both v out + and v out C benefits regula- tion in high current applications and/or applications having electrical interconnection losses. the ampmd pin allows selection of internal precision feedback resis- tors for high common mode rejection differencing appli- cations, or direct access to the actual amplifier inputs without these internal feedback resistors for other appli- cations. the ampmd pin is grounded to connect the internal precision resistors in a unity-gain differencing application or tied to the intv cc pin to bypass the internal resistors and make the amplifier inputs directly available. the amplifier is a unity-gain stable, 2mhz gain-band- width, >120db open-loop gain design. the amplifier has an output slew rate of 5v/ m s and is capable of driving capacitive loads with an output rms current typically up to 25ma. the amplifier is not capable of sinking current and therefore must be resistively loaded to do so. output overvoltage protection an overvoltage comparator, 0v, guards against transient overshoots (>10%) as well as other more serious condi- tions that may overvoltage the output. in this case, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. power good (pgood) the pgood pin is connected to the drain of an internal mosfet. the mosfet turns on when the output voltage is not within 10% of its nominal output level as deter- mined by the feedback divider. when the output is within 10% of its nominal value, the mosfet is turned off within 10 m s and the pgood pin should be pulled up by an external resistor to a source of up to 7v. short-circuit detection the run/ss capacitor is used initially to limit the inrush current from the input power source. once the control- lers have been given time, as determined by the capacitor on the run/ss pin, to charge up the output capacitors and provide full-load current, the run/ss capacitor is then used as a short-circuit timeout circuit. if the output voltage falls to less than 70% of its nominal output voltage the run/ss capacitor begins discharging as- suming that the output is in a severe overcurrent and/or short-circuit condition. if the condition lasts for a long enough period as determined by the size of the run/ss capacitor, the controller will be shut down until the run/ss pin voltage is recycled. this built-in latchoff can be overidden by providing a current >5 m a at a compli- ance of 5v to the run/ss pin. this current shortens the soft-start period but also prevents net discharge of the
12 ltc3716 applicatio s i for atio wu u u the basic ltc3716 application circuit is shown in figure 1 on the first page. external component selection begins with the selection of the inductor(s) based on ripple current requirements and continues with the r sense1, 2 resistor selection using the calculated peak inductor current and/or maximum current limit. next, the power mosfets and d1 and d2 are selected. the oper- ating frequency and the inductor are chosen based mainly on the amount of ripple current. finally, c in is selected for its ability to handle the input ripple current (that polyphase tm operation minimizes) and c out is chosen with low enough esr to meet the output ripple voltage and load step specifications (also minimized with polyphase). current mode architecture provides inherent current sharing between output stages. the circuit shown in figure 1 can be configured for operation up to an input voltage of 28v (limited by the external mosfets). current mode control allows the ability to connect the two output stages to two different input power supply rails. a heavy output load can take some power from each input supply according to the selection of the r sense resistors. r sense selection for output current r sense1, 2 are chosen based on the required peak output current. the ltc3716 current comparator has a maxi- mum threshold of 75mv/r sense and an input common mode range of sgnd to 1.1(intv cc ). the current com- parator threshold sets the peak inductor current, yielding a maximum average output current i max equal to the peak value less half the peak-to-peak ripple current, d i l . assuming a common input power source for each output stage and allowing a margin for variations in the ltc3716 and external component values yields: r sense = 2(50mv/i max ) operating frequency the ltc3716 uses a constant frequency, phase-lockable architecture with the frequency determined by an internal capacitor. this capacitor is charged by a fixed current plus an additional current which is proportional to the voltage applied to the pllfltr pin. refer to phase- locked loop and frequency synchronization for addi- tional information. a graph for the voltage applied to the pllfltr pin vs frequency is given in figure 2. as the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see efficiency considerations). the maximum switching frequency is approximately 310khz. figure 2. operating frequency vs v pllfltr operating frequency (khz) 120 170 220 270 320 pllfltr pin voltage (v) 3716 f02 2.5 2.0 1.5 1.0 0.5 0 inductor value calculation and output ripple current the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. so why would anyone ever choose to operate at lower frequencies with larger components? the answer is efficiency. a higher frequency generally results in lower efficiency because mosfet gate charge and transition losses increase run/ss capacitor during a severe overcurrent and/or short-circuit condition. foldback current limiting is acti- vated when the output voltage falls below 70% of its operatio u (refer to functional diagram) nominal level whether or not the short-circuit latchoff circuit is enabled. polyphase is a registered trademark of linear technology corporation.
13 ltc3716 directly with frequency. in addition to this basic tradeoff, the effect of inductor value on ripple current and low current operation must also be considered. the polyphase approach reduces both input and output ripple currents while optimizing individual output stages to run at a lower fundamental frequency, enhancing efficiency. the inductor value has a direct effect on ripple current. the inductor ripple current d i l per individual section, n, decreases with higher inductance or frequency and increases with higher v in or v out : d i v fl v v l out out in =- ? ? ? ? 1 where f is the individual output stage operating frequency. in a 2-phase converter, the net ripple current seen by the output capacitor is much smaller than the individual inductor ripple currents due to ripple cancellation. the details on how to calculate the net output ripple current can be found in application note 77. figure 3 shows the net ripple current seen by the output capacitors for the 1- and 2- phase configurations. the output ripple current is plotted for a fixed output voltage as the duty factor is varied between 10% and 90% on the x-axis. the output ripple current is normalized against the inductor ripple current at zero duty factor. the graph can be used in place of tedious calculations, simplifying the design process. accepting larger values of d i l allows the use of low inductances, but can result in higher output voltage ripple. a reasonable starting point for setting ripple current is d i l = 0.4(i out )/2, where i out is the total load current. remember, the maximum d i l occurs at the maximum input voltage. the individual inductor ripple currents are determined by the inductor, input and output voltages. inductor core selection once the values for l1 and l2 are known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy, or kool m m ? cores. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as induc- tance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con- centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc- tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! molypermalloy (from magnetics, inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. a reasonable compromise from the same manufacturer is kool m m . toroids are very space effi- cient, especially when you can use several layers of wire. because they lack a bobbin, mounting is more difficult. however, designs for surface mount are available which do not increase the height significantly. power mosfet, d1 and d2 selection two external power mosfets must be selected for each output stage with the ltc3716: one n-channel mosfet for the top (main) switch, and one n-channel mosfet for the bottom (synchronous) switch. the peak-to-peak drive levels are set by the intv cc voltage. this voltage is typically 5v during start-up applicatio s i for atio wu u u kool m m is a registered trademark of magnetics, inc. figure 3. normalized output ripple current vs duty factor [i rms ? 0.3 ( d i o(pCp) )] duty factor (v out /v in ) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 3716 f03 2-phase 1-phase ? i o(p-p) v o /fl
14 ltc3716 (see extv cc pin connection). consequently, logic-level threshold mosfets must be used in most applications. the only exception is if low input voltage is expected (v in < 5v); then, sublogic-level threshold mosfets (v gs(th) < 1v) should be used. pay close attention to the bv dss specification for the mosfets as well; most of the logic-level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on resistance r ds(on) , reverse transfer capacitance c rss , input voltage and maximum output current. when the ltc3716 is operating in continuous mode the duty factors for the top and bottom mosfets of each output stage are given by: main switch duty cycle v v out in = synchronous switch duty cycle vv v in out in = ? ? ? ? the mosfet power dissipations at maximum output current are given by: p v v i r kv i cf main out in max ds on in max rss = ? ? ? ? + () + () ? ? ? ? ()() 2 1 2 2 2 d () p vv v i r sync in out in max ds on = ? ? ? ? + () () 2 1 2 d where d is the temperature dependency of r ds(on) and k is a constant inversely related to the gate drive current. both mosfets have i 2 r losses but the topside n-channel equation includes an additional term for transition losses, which peak at the highest input voltage. for v in < 20v the high current efficiency generally improves with larger mosfets, while for v in > 20v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c rss actual provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. the term (1 + d ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but d = 0.005/ c can be used as an approximation for low voltage mosfets. c rss is usually specified in the mosfet characteristics. the constant k = 1.7 can be used to estimate the contributions of the two terms in the main switch dissipation equation. the schottky diodes, d1 and d2 shown in figure 1 conduct during the dead-time between the conduction of the two large power mosfets. this helps prevent the body diode of the bottom mosfet from turning on, storing charge during the dead-time, and requiring a reverse recovery period which would reduce efficiency. a 1a to 3a schottky (depending on output current) diode is generally a good compromise for both regions of opera- tion due to the relatively small average current. larger diodes result in additional transition losses due to their larger junction capacitance. c in and c out selection in continuous mode, the source current of each top n-channel mosfet is a square wave of duty cycle v out / v in . a low esr input capacitor sized for the maximum rms current must be used. the details of a closed form equation can be found in application note 77. figure 4 shows the input capacitor ripple current for a 2-phase configuration with the output voltage fixed and input voltage varied. the input ripple current is normalized against the dc output current. the graph can be used in place of tedious calculations. the minimum input ripple current can be achieved when the input voltage is twice the output voltage. in the graph of figure 4, the 2-phase local maximum input rms capacitor currents are reached when: v v k out in = - 21 4 where k = 1, 2 these worst-case conditions are commonly used for design because even significant deviations do not offer applicatio s i for atio wu u u
15 ltc3716 much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the capacitor manufacturer if there is any question. the output ripple varies with input voltage since d i l is a function of input voltage. the output ripple will be less than 50mv at max v in with d i l = 0.4i out(max) /2 assuming: c out required esr < 4(r sense ) and c out > 1/(16f)(r sense ) the emergence of very low esr capacitors in small, surface mount packages makes very physically small implementations possible. the ability to externally com- pensate the switching regulator loop using the i th pin(opti-loop compensation) allows a much wider se- lection of output capacitor types. opti-loop compensa- tion effectively removes constraints on output capacitor esr. the impedance characteristics of each capacitor type are significantly different than an ideal capacitor and therefore require accurate modeling or bench evaluation during design. manufacturers such as nichicon, united chemicon and sanyo should be considered for high performance through-hole capacitors. the os-con semiconductor dielectric capacitor available from sanyo and the panasonic sp surface mount types have the lowest (esr)(size) product of any aluminum electrolytic at a somewhat higher price. an additional ceramic capacitor in parallel with os-con type capacitors is recommended to reduce the inductance effects. in surface mount applications, multiple capacitors may have to be paralleled to meet the esr or rms current handling requirements of the application. aluminum elec- trolytic and dry tantalum capacitors are both available in surface mount configurations. new special polymer sur- face mount capacitors offer very low esr also but have much lower capacitive density per unit volume. in the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. several excellent choices are the avx tps, avx tpsv or the kemet t510 series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. other capacitor types include sanyo os-con, nichicon pl series and sprague 595d series. consult the manufacturer for other specific recommendations. a combination of capacitors will often result in maximizing performance and minimizing overall cost and size. applicatio s i for atio wu u u figure 4. normalized rms input ripple current vs duty factor for 1 and 2 output stages duty factor (v out /v in ) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.6 0.5 0.4 0.3 0.2 0.1 0 3716 f04 rms input ripple currnet dc load current 2-phase 1-phase it is important to note that the efficiency loss is propor- tional to the input rms current squared and therefore a 2-phase implementation results in 75% less power loss when compared to a single phase design. battery/input protection fuse resistance (if used), pc board trace and connector resistance losses are also reduced by the reduction of the input ripple current in a 2-phase system. the required amount of input capacitance is further reduced by the factor, 2, due to the effective increase in the frequency of the current pulses. the selection of c out is driven by the required effective series resistance (esr). typically once the esr require- ment has been met, the rms current rating generally far exceeds the i ripple(p-p) requirements. the steady state output ripple ( d v out ) is determined by: dd v i esr fc out ripple out ?+ ? ? ? ? 1 16 where f = operating frequency of each stage, c out = output capacitance and d i ripple = combined inductor ripple currents.
16 ltc3716 intv cc regulator an internal p-channel low dropout regulator produces 5v at the intv cc pin from the v in supply pin. the intv cc regulator powers the drivers and internal circuitry of the ltc3716. the intv cc pin regulator can supply up to 50ma peak and must be bypassed to power ground with a minimum of 4.7 m f tantalum or electrolytic capacitor. an additional 1 m f ceramic capacitor placed very close to the ic is recommended due to the extremely high instanta- neous currents required by the mosfet gate drivers. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi- mum junction temperature rating for the ltc3716 to be exceeded. the supply current is dominated by the gate charge supply current, in addition to the current drawn from the differential amplifier output. the gate charge is dependent on operating frequency as discussed in the efficiency considerations section. the supply current can either be supplied by the internal 5v regulator or via the extv cc pin. when the voltage applied to the extv cc pin is less than 4.7v, all of the intv cc load current is supplied by the internal 5v linear regulator. power dissipation for the ic is higher in this case by (i in )(v in C intv cc ) and efficiency is lowered. the junction temperature can be estimated by using the equations given in note 1 of the electrical characteristics. for example, the ltc3716 v in current is limited to less than 24ma from a 24v supply: t j = 70 c + (24ma)(24v)(85 c/w) = 119 c use of the extv cc pin reduces the junction temperature to: t j = 70 c + (24ma)(5v)(85 c/w) = 80.2 c the input supply current should be measured while the controller is operating in continuous mode at maximum v in and the power dissipation calculated in order to prevent the maximum junction temperature from being exceeded. extv cc connection the ltc3716 contains an internal p-channel mosfet switch connected between the extv cc and intv cc pins. when the voltage applied to extv cc rises above 4.7v, the internal regulator is turned off and an internal switch closes, connecting the extv cc pin to the intv cc pin thereby supplying internal and mosfet gate driving power to the ic. the switch remains closed as long as the voltage applied to extv cc remains above 4.5v. this allows the mosfet driver and control power to be derived from the output during normal operation (4.7v < v extvcc < 7v) and from the internal regulator when the output is out of regulation (start-up, short-circuit). do not apply greater than 7v to the extv cc pin and ensure that extv cc < v in + 0.3v when using the application circuits shown. if an external voltage source is applied to the extv cc pin when the v in supply is not present, a diode can be placed in series with the ltc3716s v in pin and a schottky diode between the extv cc and the v in pin, to prevent current from backfeeding v in . significant efficiency gains can be realized by powering intv cc from the output, since the v in current resulting from the driver and control currents will be scaled by the ratio: (duty factor)/(efficiency). for 5v regulators this means connecting the extv cc pin directly to v out . how- ever, for 3.3v and other lower voltage regulators, addi- tional supply circuitry is required to derive intv cc power from the output. the following list summarizes the four possible connec- tions for extv cc: 1. extv cc left open (or grounded). this will cause intv cc to be powered from the internal 5v regulator resulting in a significant efficiency penalty at high input voltages. 2. extv cc connected directly to v out . this is the normal connection for a 5v regulator and provides the highest efficiency. 3. extv cc connected to an external supply. if an external supply is available in the 5v to 7v range, it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements. 4. extv cc connected to an output-derived boost network. for 3.3v and other low voltage regulators, efficiency gains can still be realized by connecting extv cc to an output- derived voltage which has been boosted to greater than 4.7v but less than 7v. this can be done with either the inductive boost winding as shown in figure 5a or the capacitive charge pump shown in figure 5b. the charge pump has the advantage of simple magnetics. applicatio s i for atio wu u u
17 ltc3716 topside mosfet driver supply (c b ,d b ) (refer to functional diagram) external bootstrap capacitors c b1 and c b2 connected to the boost1 and boost2 pins supply the gate drive voltages for the topside mosfets. capacitor c b in the functional diagram is charged though diode d b from intv cc when the sw pin is low. when the topside mosfet turns on, the driver places the c b voltage across the gate- source of the desired mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v in and the boost pin rises to v in + v intvcc . the value of the boost capacitor c b needs to be 30 to 100 times that of the total input capacitance of the topside mosfet(s). the reverse breakdown of d b must be greater than v in(max). the final arbiter when defining the best gate drive ampli- tude level will be the input supply current. if a change is made that decreases input current, the efficiency has improved. if the input current does not change then the efficiency has not changed either. output voltage the ltc3716 has a true remote voltage sense capablity. the sensing connections should be returned from the load back to the differential amplifiers inputs through a com- mon, tightly coupled pair of pc traces. the differential amplifier corrects for dc drops in both the power and ground paths. the differential amplifier output signal is applicatio s i for atio wu u u divided down and compared with the internal precision 0.6v voltage reference by the error amplifier. output voltage programming the output voltage is digitally programmed as defined in table 1 using the vid0 to vid4 logic input pins. the vid logic inputs program a precision, 0.25% internal feedback resistive divider. the ltc3716 has an output voltage range of 0.6v to 1.75v in 25mv and 50mv steps. between the attenout pin and ground is a variable resistor, r1, whose value is controlled by the five vid input pins (vid0 to vid4). another resistor, r2, between the attenin and the attenout pins completes the resistive divider. the output voltage is thus set by the ratio of (r1 + r2) to r1. each vid digital input is pulled up by a 40k resistor in series with a diode from v bias . therefore, it must be grounded to get a digital low input, and can be either floated or connected to v bias to get a digital high input. the series diode is used to prevent the digital inputs from being damaged or clamped if they are driven higher than v bias . the digital inputs accept cmos voltage levels. v bias is the supply voltage for the vid section. it is normally connected to intv cc but can be driven from other sources. if it is driven from another source, that source must be in the range of 2.7v to 5.5v and must be alive prior to enabling the ltc3716. figure 5a. secondary output loop with extv cc connection figure 5b. capacitive charge pump for extv cc 3716 f05a v in tg1 n-ch 1n4148 n-ch bg1 fcb r6 r5 pgnd ltc3716 sw1 extv cc optional extv cc connection 5v < v sec < 7v t1 r sense v sec v out v in + c in + 1 f + c out 4 3 2 1 3716 f05b v in tg1 n-ch n-ch bg1 pgnd ltc3716 sw1 extv cc l1 r sense bat85 bat85 bat85 0.22 f v out v in + c in + + c out vn2222ll 4 3 2 1
18 ltc3716 applicatio s i for atio wu u u soft-start/run function the run/ss pin provides three functions: 1) run/shut- down, 2) soft-start and 3) a defeatable short-circuit latchoff timer. soft-start reduces the input power sources surge currents by gradually increasing the controllers current limit i th(max) . the latchoff timer prevents very short, extreme load transients from tripping the overcurrent table 1. vid output voltage programming vid4 vid3 vid2 vid1 vid0 ltc3716 0 0 0 0 0 1.750v 0 0 0 0 1 1.700v 0 0 0 1 0 1.650v 0 0 0 1 1 1.600v 0 0 1 0 0 1.550v 0 0 1 0 1 1.500v 0 0 1 1 0 1.450v 0 0 1 1 1 1.400v 0 1 0 0 0 1.350v 0 1 0 0 1 1.300v 0 1 0 1 0 1.250v 0 1 0 1 1 1.200v 0 1 1 0 0 1.150v 0 1 1 0 1 1.100v 0 1 1 1 0 1.050v 0 1 1 1 1 1.000v 1 0 0 0 0 0.975v 1 0 0 0 1 0.950v 1 0 0 1 0 0.925v 1 0 0 1 1 0.900v 1 0 1 0 0 0.875v 1 0 1 0 1 0.850v 1 0 1 1 0 0.825v 1 0 1 1 1 0.800v 1 1 0 0 0 0.775v 1 1 0 0 1 0.750v 1 1 0 1 0 0.725v 1 1 0 1 1 0.700v 1 1 1 0 0 0.675v 1 1 1 0 1 0.650v 1 1 1 1 0 0.625v 1 1 1 1 1 0.600v latch. a small pull-up current (>5 m a) supplied to the run/ ss pin will prevent the overcurrent latch from operating. the following explanation describes how the functions operate. an internal 1.2 m a current source charges up the soft-start capacitor, c ss . when the voltage on run/ss reaches 1.5v, the controller is permitted to start operating. as the voltage on run/ss increases from 1.5v to 3.0v, the internal current limit is increased from 25mv/r sense to 75mv/ r sense . the output current limit ramps up slowly, taking an additional 1.4s/ m f to reach full current. the output current thus ramps up slowly, reducing the starting surge current required from the input power supply. if run/ss has been pulled all the way to ground there is a delay before starting of approximately: t v a csfc delay ss ss = m =m () 15 12 125 . . ./ the time for the output current to ramp up is then: t vv a csfc iramp ss ss = - m =m () 315 12 125 . . ./ by pulling the run/ss pin below 0.8v the ltc3716 is put into low current shutdown (i q < 40 m a). the run/ss pins can be driven directly from logic as shown in figure 6. diode d1 in figure 6 reduces the start delay but allows c ss to ramp up slowly providing the soft-start function. the run/ss pin has an internal 6v zener clamp (see functional diagram). figure 6. run/ss pin interfacing 3.3v or 5v run/ss v in intv cc run/ss d1 d1* c ss r ss * c ss r ss * 3716 f06 *optional to defeat overcurrent latchoff
19 ltc3716 the value of the soft-start capacitor c ss may need to be scaled with output voltage, output capacitance and load current characteristics. the minimum soft-start capaci- tance is given by: c ss > (c out )(v out )(10 -4 )(r sense ) the minimum recommended soft-start capacitor of c ss = 0.1 m f will be sufficient for most applications. phase-locked loop and frequency synchronization the ltc3716 has a phase-locked loop comprised of an internal voltage controlled oscillator and phase detector. this allows the top mosfet turn-on to be locked to the rising edge of an external source. the frequency range of the voltage controlled oscillator is 50% around the center frequency f o . a voltage applied to the pllfltr pin of 1.2v corresponds to a frequency of approximately 220khz. the nominal operating frequency range of the ltc3716 is 140khz to 310khz. the phase detector used is an edge sensitive digital type which provides zero degrees phase shift between the external and internal oscillators. this type of phase detec- tor will not lock up on input frequencies close to the harmonics of the vco center frequency. the pll hold-in range, d f h , is equal to the capture range, d f c: d f h = d f c = 0.5 f o (150khz-300khz) the output of the phase detector is a complementary pair of current sources charging or discharging the external filter network on the pllfltr pin. a simplified block diagram is shown in figure 7. applicatio s i for atio wu u u fault conditions: overcurrent latchoff the run/ss pin also provides the ability to latch off the controllers when an overcurrent condition is detected. the run/ss capacitor, c ss , is used initially to limit the inrush current of both controllers. after the controllers have been started and been given adequate time to charge up the output capacitors and provide full load current, the run/ ss capacitor is used for a short-circuit timer. if the output voltage falls to less than 70% of its nominal value after c ss reaches 4.1v, c ss begins discharging on the assumption that the output is in an overcurrent condition. if the condition lasts for a long enough period as determined by the size of the c ss , the controller will be shut down until the run/ss pin voltage is recycled. if the overload occurs during start-up, the time can be approximated by: t lo1 ? (c ss ? 0.6v)/(1.2 m a) = 5 ? 10 5 (c ss ) if the overload occurs after start-up, the voltage on c ss will continue charging and will provide additional time before latching off: t lo2 ? (c ss ? 3v)/(1.2 m a) = 2.5 ? 10 6 (c ss ) this built-in overcurrent latchoff can be overridden by providing a pull-up resistor, r ss , to the run/ss pin as shown in figure 6. this resistance shortens the soft-start period and prevents the discharge of the run/ss capaci- tor during a severe overcurrent and/or short-circuit con- dition. when deriving the 5 m a current from v in as in the figure, current latchoff is always defeated. the diode connecting this pull-up resistor to intv cc , as in figure 6, eliminates any extra supply current during shutdown while eliminating the intv cc loading from preventing controller start-up. why should you defeat current latchoff? during the prototyping stage of a design, there may be a problem with noise pickup or poor layout causing the protection circuit to latch off the controller. defeating this feature allows troubleshooting of the circuit and pc layout. the internal short-circuit and foldback current limiting still remains active, thereby protecting the power supply system from failure. a decision can be made after the design is com- plete whether to rely solely on foldback current limiting or to enable the latchoff feature by removing the pull-up resistor. figure 7. phase-locked loop block diagram external osc 2.4v r lp 10k c lp osc digital phase/ frequency detector phase detector pllin 3716 f07 pllfltr 50k
20 ltc3716 if the external frequency (f pllin ) is greater than the oscil- lator frequency f 0sc , current is sourced continuously, pulling up the pllfltr pin. when the external frequency is less than f 0sc , current is sunk continuously, pulling down the pllfltr pin. if the external and internal fre- quencies are the same but exhibit a phase difference, the current sources turn on for an amount of time correspond- ing to the phase difference. thus the voltage on the pllfltr pin is adjusted until the phase and frequency of the external and internal oscillators are identical. at this stable operating point the phase comparator output is open and the filter capacitor c lp holds the voltage. the ltc3716 pllin pin must be driven from a low impedance source such as a logic gate located close to the pin. the loop filter components (c lp , r lp ) smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. the filter components c lp and r lp determine how fast the loop acquires lock. typically r lp =10k and c lp is 0.01 m f to 0.1 m f. minimum on-time considerations minimum on-time, t on(min) , is the smallest time duration that the ltc3716 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t v vf on min out in () < () if the duty cycle falls below what can be accommodated by the minimum on-time, the ltc3716 will begin to skip cycles resulting in variable frequency operation. the out- put voltage will continue to be regulated, but the ripple current and ripple voltage will increase. the minimum on-time for the ltc3716 is generally less than 200ns. however, as the peak sense voltage de- creases, the minimum on-time gradually increases. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with corre- spondingly larger ripple current and voltage ripple. if an application can operate close to the minimum on-time limit, an inductor must be chosen that has a low enough inductance to provide sufficient ripple amplitude to meet the minimum on-time requirement. as a general rule, keep the inductor ripple current of each phase equal to or greater than 15% of i out(max) at v in(max) . fcb pin operation the fcb pin can be used to regulate a secondary winding or as a logic level input. continuous operation is forced when the fcb pin drops below 0.6v. during continuous mode, current flows continuously in the transformer pri- mary. the secondary winding(s) supply current only when the bottom, synchronous switch is on. when primary load currents are low and/or the v in /v out ratio is low, the synchronous switch may not be on for a sufficient amount of time to transfer power from the output capacitor to the secondary load. forced continuous operation will support secondary windings providing there is sufficient synchro- nous switch duty factor. thus, the fcb input pin removes the requirement that power must be drawn from the inductor primary in order to extract power from the auxiliary winding(s). with the loop in continuous mode, the auxiliary output(s) may nominally be loaded without regard to the primary output load. the secondary output voltage v sec is normally set as shown in figure 5a by the turns ratio n of the transformer: v sec @ (n + 1) v out however, if the controller goes into burst mode operation and halts switching due to a light primary load current, then v sec will droop. an external resistive divider from v sec to the fcb pin sets a minimum voltage v sec(min) : vv r r sec min () . ?+ ? ? ? ? 06 1 6 5 where r5 and r6 are shown in figure 5a. if v sec drops below this level, the fcb voltage forces temporary continuous switching operation until v sec is again above its minimum. applicatio s i for atio wu u u
21 ltc3716 in order to prevent erratic operation if no external connec- tions are made to the fcb pin, the fcb pin has a 0.18 m a internal current source pulling the pin high. include this current when choosing resistor values r5 and r6. the following table summarizes the possible states avail- able on the fcb pin: table 2 fcb pin condition 0v to 0.55v forced continuous (current reversal allowedburst inhibited) 0.65v < v fcb < 4.3v minimum peak current induces burst mode operation no current reversal allowed feedback resistors regulating a secondary winding >4.8v burst mode operation disabled constant frequency mode enabled no current reversal allowed no minimum peak current active voltage positioning active voltage positioning can be used to minimize peak- to-peak output voltage excursion under worst-case tran- sient loading conditions. the open-loop dc gain of the control loop is reduced depending upon the maximum load step specifications. active voltage positioning can easily be added to the ltc3716 by loading the i th pin with a resistive divider having a thevenin equivalent voltage source equal to the midpoint operating voltage of the error amplifier, or 1.2v (see figure 8). applicatio s i for atio wu u u figure 8. active voltage positioning applied to the ltc3716 i th r c r t1 intv cc c c 3716 f08 ltc3716 r t2 the resistive load reduces the dc loop gain while main- taining the linear control range of the error amplifier. the worst-case peak-to-peak output voltage deviation due to transient loading can theoretically be reduced to half or alternatively the amount of output capacitance can be reduced for a particular application. a complete explanation is included in design solutions 10 or the ltc1736 data sheet. (see www.linear-tech.com) efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: %efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc3716 circuits: 1) i 2 r losses, 2) topside mosfet transition losses, 3) intv cc regulator current and 4) ltc3716 v in current (including loading on the differential amplifier output). 1) i 2 r losses are predicted from the dc resistances of the fuse (if used), mosfet, inductor, current sense resistor, and input and output capacitor esr. in continuous mode the average output current flows through l and r sense , but is chopped between the topside mosfet and the synchronous mosfet. if the two mosfets have approxi- mately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l, r sense and esr to obtain i 2 r losses. for example, if each r ds(on) = 10m w , r l = 10m w , and r sense = 5m w , then the total resistance is 25m w . this results in losses ranging from 2% to 8% as the output current increases from 3a to 15a per output stage for a 5v output, or a 3% to 12% loss per output stage for a 3.3v output. efficiency varies as the inverse square of v out for the same external components and output power level. the combined effects of increas- ingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 2) transition losses apply only to the topside mosfet(s), and are significant only when operating at high input
22 ltc3716 voltages (typically 12v or greater). transition losses can be estimated from: transition loss v i cf in o max rss = ? ? ? ? (. ) () 17 2 2 3) intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = (q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. supplying intv cc power through the extv cc switch input from an output-derived source will scale the v in current required for the driver and control circuits by the ratio (duty factor)/(efficiency). for example, in a 20v to 5v application, 10ma of intv cc current results in approxi- mately 3ma of v in current. this reduces the mid-current loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 4) the v in current has two components: the first is the dc supply current given in the electrical characteristics table, which excludes mosfet driver and control cur- rents; the second is the current drawn from the differential amplifier output. v in current typically results in a small (<0.1%) loss. other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. it is very important to include these system level losses in the design of a system. the internal battery and input fuse resistance losses can be minimized by making sure that c in has adequate charge storage and a very low esr at the switching frequency. a 50w supply will typically require a minimum of 200 m f to 300 m f of output capaci- tance having a maximum of 10m w to 20m w of esr. the ltc3716 2-phase architecture typically halves the input and output capacitance requirements over competing solutions. other losses including schottky conduction applicatio s i for atio wu u u losses during dead-time and inductor core losses gener- ally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to d i load (esr), where esr is the effective series resistance of c out ( d i load ) also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. the availability of the i th pin not only allows optimization of control loop behavior but also provides a dc coupled and ac filtered closed loop response test point. the dc step, rise time, and settling at this test point truly reflects the closed loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the figure 1 circuit will provide an adequate starting point for most applications. the i th series r c -c c filter sets the dominant pole-zero loop compensation. the values can be modified slightly (from 0.2 to 5 times their suggested values) to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be decided upon first because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of <2 m s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the ith pin signal which is in the feedback loop and is the filtered and compensated control loop response. the gain of the loop will be increased by
23 ltc3716 increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. automotive considerations: plugging into the cigarette lighter as battery-powered devices go mobile, there is a natural interest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during opera- applicatio s i for atio wu u u figure 9. automotive application protection v in 3716 f09 12v 50a i pk rating transient voltage suppressor general instrument 1.5ka24a ltc3716 tion. but before you connect, be advised: you are plugging into the supply from hell. the main battery line in an automobile is the source of a number of nasty potential transients, including load-dump, reverse-battery, and double-battery. load-dump is the result of a loose battery cable. when the cable breaks connection, the field collapse in the alternator can cause a positive spike as high as 60v which takes several hundred milliseconds to decay. reverse-battery is just what it says, while double-battery is a consequence of tow truck operators finding that a 24v jump start cranks cold engines faster than 12v. the network shown in figure 9 is the most straightfor- ward approach to protect a dc/dc converter from the ravages of an automotive power line. the series diode prevents current from flowing during reverse-battery, while the transient suppressor clamps the input voltage during load-dump. note that the transient suppressor should not conduct during double-battery operation, but must still clamp the input voltage below breakdown of the converter. although the lt3716 has a maximum input voltage of 36v, most applications will be limited to 30v by the mosfet bv dss . design example as a design example, assume v in = 5v (nominal), v in = 5.5v (max), v out = 1.2v, i max = 20a, t a = 70 c and f = 300khz. the inductance value is chosen first based on a 30% ripple current assumption. the highest value of ripple current occurs at the maximum input voltage. tie the freqset pin to the intv cc pin for 300khz operation. the minimum inductance for 30% ripple current is: l v fl v v v khz a v v h out out in 3 d () - ? ? ? ? 3 ()()() - ? ? ? ? 3m 1 12 300 30 10 1 12 55 104 . % . . . a 1 m h inductor will produce 31% ripple current. the peak inductor current will be the maximum dc value plus one half the ripple current, or 11.5a. the minimum on-time occurs at maximum v in : t v vf v v khz s on min out in () == ()( ) =m 12 5 5 300 073 . . . the r sense resistors value can be calculated by using the maximum current sense voltage specification with some accomodation for tolerances: r mv a sense =?w 50 11 5 0 004 . . the power dissipation on the topside mosfet can be easily estimated. using a siliconix si4420dy for example; r ds(on) = 0.013 w , c rss = 300pf. at maximum input voltage with t j (estimated) = 110 c at an elevated ambient temperature:
24 ltc3716 applicatio s i for atio wu u u p v v cc vapf khz w main = () + () - () [] + ()()( ) () = 12 55 10 1 0 005 110 25 0 013 1 7 5 5 10 300 300 0 45 2 2 . . . ... . w the worst-case power disipated by the synchronous mosfet under normal operating conditions at elevated ambient temperature and estimated 50 c junction tem- perature rise is: p vv v a w sync = - ()( ) w () = 55 12 55 2 10 1 48 0 013 15 2 .. . .. . a short-circuit to ground will result in a folded back current of about: i mv ns v h a sc = w + () m ? ? = 25 0 004 1 2 200 5 5 1 68 . . . the worst-case power disipated by the synchronous mosfet under short-circuit conditions at elevated ambi- ent temperature and estimated 50 c junction temperature rise is: p vv v a mw sync = - ()() w () = 55 12 55 68 148 0013 696 2 .. . ... which is less than normal, full-load conditions. inciden- tally, since the load no longer dissipates power in the shorted condition, total system power dissipation is de- creased by over 99%. the duty factor for this application is: df v v v v o in == = 12 5 024 . . using figure 4, the rms ripple current will be: i inrms = (20a)(0.25) = 5a rms an input capacitor(s) with a 5a rms ripple current rating is required. the output capacitor ripple current is calculated by using the inductor ripple already calculated for each inductor and multiplying by the factor obtained from figure 3 along with the calculated duty factor. the output ripple in con tinuous mode will be highest at the maximum input voltage since the duty factor is < 50%. the maximum output current ripple is: d d i v fl at d f i v khz h a vmamv cout out coutmax pp outripple p p p p = () = () m () = =w () = - -- 05 24 12 300 1 0 05 2 20 2 40 .% . . . pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3716. check the following in your layout: 1) are the signal and power grounds separate? the signal ground traces should return to pin 9 first. connect pin 9 to pin 28 through a wide and straight trace. then the signal ground joins the power ground plane beside pin 28. it is recommended that the pin 28 return to the (C) plates of c in . sense + sense trace to inductor trace to output cap (+) 3716 f09b figure 10. proper current sense connections 2) does the ltc3716 v os + pin connect to the point of load? does the ltc3716 v os C pin connect to the load return?
25 ltc3716 applicatio s i for atio wu u u 3) are the sense C and sense + leads routed together with minimum pc trace spacing? the filter capacitors between sense + and sense C pin pairs should be as close as possible to the ltc3716. ensure accurate current sensing with kelvin connections at the current sense resistor. see figure 10. 4) does the (+) plate of c in connect to the drains of the topside mosfets as closely as possible? this capacitor provides the ac current to the mosfets. keep the input current path formed by the input capacitor, top and bottom mosfets, and the schottky diode on the same side of the pc board in a tight loop to minimize conducted and radiated emi. 5) is the intv cc 1 m f ceramic decoupling capacitor con- nected closely between intv cc and the pgnd pin? this capacitor carries the mosfet driver peak currents. a small value is recommended to allow placement immedi- ately adjacent to the ic. 6) keep the switching nodes, sw1 (sw2), away from sensitive small-signal nodes. ideally the switch nodes should be placed at the furthest point from the ltc3716. 7) use a low impedance source such as a logic gate to drive the pllin pin and keep the lead as short as possible. the diagram in figure 11 illustrates all branch currents in a 2-phase switching regulator. it becomes very clear after studying the current waveforms why it is critical to keep the high-switching-current paths to a small physical size. high electric and magnetic fields will radiate from these loops just as radio stations transmit signals. the output capacitor ground should return to the negative terminal of the input capacitor and not share a common ground path with any switched current paths. the left half of the circuit gives rise to the noise generated by a switching regula- tor. the ground terminations of the sychronous mosfets and schottky diodes should return to the negative plate(s) r l v out c out + d1 l1 sw1 r sense1 v in c in r in + d2 bold lines indicate high, switching current lines. keep lines to a minimum length. l2 sw2 3716 f10 r sense2 figure 11. instantaneous current path flow in a multiple phase switching regulator
26 ltc3716 applicatio s i for atio wu u u of the input capacitor(s) with a short isolated pc trace since very high switched currents are present. a separate isolated path from the negative plate(s) of the input capacitor(s) should be used to tie in the ic power ground pin (pgnd) and the signal ground pin (sgnd). this technique keeps inherent signals generated by high cur- rent pulses from taking alternate current paths that have finite impedances during the total period of the switching regulator. external opti-loop compensation allows over- compensation for pc layouts which are not optimized but this is not the recommended design procedure. simplified visual explanation of how a 2-phase controller reduces both input and output rms ripple current a multiphase power supply significantly reduces the amount of ripple current in both the input and output capacitors. the rms input ripple current is divided by, and the effective ripple frequency is multiplied up by the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). the output ripple amplitude is also reduced by, and the effective ripple frequency is increased by the number of phases used. figure 12 graphically illustrates the principle. figure 12. single and 2-phase current waveforms voltage. the worst-case rms ripple current for a two stage design results in peak outputs of 1/4 and 3/4 of input voltage. when the rms current is calculated, higher effective duty factor results and the peak current levels are divided as long as the currents in each stage are balanced. refer to application note 19 for a detailed description of how to calculate rms current for the single stage switch- ing regulator. figures 3 and 4 illustrate how the input and output currents are reduced by using an additional phase. the input current peaks drop in half and the frequency is doubled for this 2-phase converter. the input capacity requirement is thus reduced theoretically by a factor of four! ceramic input capacitors with their unbeatably low esr characteristics can be used. figure 4 illustrates the rms input current drawn from the input capacitance vs the duty cycle as determined by the ratio of input and output voltage. the peak input rms current level of the single phase system is reduced by 50% in a 2-phase solution due to the current splitting between the two stages. an interesting result of the 2-phase solution is that the v in which produces worst-case ripple current for the input capacitor, v out = v in /2, in the single phase design pro- duces zero input current ripple in the 2-phase design. the output ripple current is reduced significantly when compared to the single phase solution using the same inductance value because the v out /l discharge current term from the stage that has its bottom mosfet on subtracts current from the (v in C v out )/l charging current resulting from the stage which has its top mosfet on. the output ripple current is: d i v fl dd d ripple out = -- () -+ ? ? 2 12 1 12 1 where d is duty factor. the input and output ripple frequency is increased by the number of stages used, reducing the output capacity requirements. when v in is approximately equal to 2(v out ) as illustrated in figures 3 and 4, very low input and output ripple currents result. i cin sw v i cout i cin sw1 v dual phase single phase sw2 v i cout ripple i l1 i l2 3216 f11 the worst-case rms ripple current for a single stage design peaks at an input voltage of twice the output
27 ltc3716 typical applicatio u figure 13. 5v to 20v input, 0.6v to 1.75v/30a power supply with active voltage positioning figure 13 shows a typical application using ltc3716 to power the mobile cpu core. the input can vary from 7v to 24v, the output voltage can be programmed from 0.6v to 1.75v with a maximum current of 30a. this power supply receives three input signals to generate different output voltage offsets based on the operation conditions. with the ampmd pin of ltc3716 tied to intvcc, the ltc3716 provides a regular operational amplifier to implement these offsets. when gmuxsel is low, the output voltage is offset C1.2% from the vid command voltage. the offset equals ra/rb. when dpslp# is low, the output voltage is decreased by approximately 4%. this offset can be in- creased by decreasing rc and will be disabled when the dprslpvr signal is high. the optional filtering circuit (q1 and q2) is used to mask the pwrgood during the vid transitions. r11 196k 1% r12 1m r13 10k r17 22k r15 39.2k, 1% 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 run/ss sense1 + sense1 eain pllfltr pllin fcb i th sgnd v diffout v os v os + sense2 sense2 + attenout attenin vid0 vid1 pgood tg1 sw1 boost1 v in bg1 extv cc intv cc pgnd bg2 boost2 sw2 tg2 ampmd v bias vid4 vid3 vid2 ltc3716 c1 1000pf c1 1 f r1 10 r5 10 r6 10 vid4 vid3 vid2 c6 0.47 f d1 bat54a d3 bat54a 3 2 1 c11 1 f c16 0.1 f c10 10 f 6v q9 irf7811 5 6 7 8 1 2 3 q10 irf7809 5 6 7 8 1 2 3 q11 irf7809 5 6 7 8 1 2 3 4 44 4 44 d4 mbrs130lt3 q3 irf7811 5 6 7 8 1 2 3 q4 irf7809 5 6 7 8 1 2 3 q5 irf7809 5 6 7 8 1 2 3 d2 mbrs130lt3 + + c out c in c in : four ceramic caps (10 f/35v) c out : four panasonic sp caps eefueod271r (270 f/2v) l1, l2: sumida cep125-1romc-h c3 1 f c14 1 f l1 1 h l2 1 h r9 0.003 r21 0.003 r25 10 gnd fb + fb c15 47pf c18 1000 f vid0 vid1 c5 0.1 f c7 0.01 f c12 0.01 f c9 1000pf c8 330pf q13 2n7002 q15 2n7002 q12 2n7002 q14 fmmt3904 r30 10k r29 100k r c 511k r b 845k r b 845k r d , 20k, 1% r a 12.1k dpslp# dprslpvr intv cc 1n4148 q2 fmmt3904 r8 10k r2 10k r3 10k r4 10k r1 10k pwrgood r23 10 r24 10 gmuxsel 3716 f12 v ron q1 fmmt3906 0.47 f 3.3v r10 3.9k optional c13, 0.47 f intv cc 2n7002 v in 5v to 20v 5v (0pt) 4 3 2 1 4 3 2 1 1 10 1 f v out
28 ltc3716 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com ? linear technology corporation 2001 related parts part number description comments ltc1438/ltc1439 dual high efficiency low noise synchronous step-down switching regulators por, auxiliary regulator ltc1438-adj dual synchronous controller with auxiliary regulator por, external feedback divider ltc1538-aux dual high efficiency low noise synchronous step-down switching regulator auxiliary regulator, 5v standby ltc1539 dual high efficiency low noise synchronous step-down switching regulator 5v standby, por, low-battery, aux regulator ltc1436a-pll high efficiency low noise synchronous step-down switching regulator adaptive power tm mode, 24-pin ssop ltc1628/ltc1628-pg dual high efficiency, 2-phase synchronous step-down switching regulator constant frequency, standby, 5v and 3. 3v ldos ltc1629/ltc1629-pg polyphase high efficiency controller expandable up to 12 phases, g-28, up to 120a ltc1929/ltc1929-pg 2-phase high efficiency controller adjustable output up to 40a, g-28 ltc1702/ltc1703 dual high efficiency, 2-phase synchronous step-down switching regulator 500khz, 25mhz gbw ltc1708-pg dual high efficiency, 2-phase synchronous step-down switching regulator 1.3v v out 3.5v, current mode ensures with 5-bit vid and power good indication accurate current sharing, 3.5v v in 36v ltc1709-7 2-phase high efficiency controller with 5-bit mobile vid and power good burst mode operation and cycle skip low indication (0.9v v out 2v) current modes, 3.5v v in 36v ltc1709-8/ltc1709-9 2-phase high efficiency controller with 5-bit vid and power good indication vid tables vrm 8.4 and vrm9.0 ltc1735 high efficiency synchronous step-down controller burst mode operation, 16-pin narrow ssop, fault protection, 3.5v v in 36v ltc1736 high efficiency synchronous step-down controller with 5-bit vid output fault protection, power good, gn-24, 3.5v v in 36v, 0.925v v out 2v adaptive power is a trademark of linear technology corporation. 3716i lt/tp 0201 2k ? printed in usa package descriptio u dimensions in inches (millimeters) unless otherwise noted. g36 ssop 1098 0.13 ?0.22 (0.005 ?0.009) 0 ?8 0.55 ?0.95 (0.022 ?0.037) 5.20 ?5.38** (0.205 ?0.212) 7.65 ?7.90 (0.301 ?0.311) 1234 5 6 7 8 9 10 11 12 14 15 16 17 18 13 12.67 ?12.93* (0.499 ?0.509) 25 26 22 21 20 19 23 24 27 28 29 30 31 32 33 34 35 36 1.73 ?1.99 (0.068 ?0.078) 0.05 ?0.21 (0.002 ?0.008) 0.65 (0.0256) bsc 0.25 ?0.38 (0.010 ?0.015) note: dimensions are in millimeters dimensions do not include mold flash. mold flash shall not exceed 0.152mm (0.006") per side dimensions do not include interlead flash. interlead flash shall not exceed 0.254mm (0.010") per side * ** g package 36-lead plastic ssop (0.209) (ltc dwg # 05-08-1640)

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